Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBS) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBS, IOBS, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBS, IOBS, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
Notably, an FPGA may include blocks of random access memory (RAM), referred to as block RAMs (BRAMs). BRAMs may comprise static RAM (SRAM), and may be dual ported (i.e., two pairs of data and address ports). BRAMs may be used to implement various memory structures, such as first-in-first-out (FIFO) memories (referred to as a FIFOs). Historically, an individual BRAM has been used to implement a single FIFO having a depth of the BRAM size (e.g., 2048 bytes). If an application requires more than one FIFO, then each additional FIFO consumes an additional BRAM. BRAMs are a scarce resource in an FPGA. Thus, use of a BRAM to implement a single FIFO becomes a limiting constraint in an application that requires more FIFOs than there are BRAMs in a given FPGA. Accordingly, there exists a need in the art for a method and apparatus that provides an increased number of FIFOs for a given set of BRAMs in an FPGA.